Successive approximation A/D converters have an extensive range of applications, because they are implemented with relatively simple circuitry, have excellent compatibility with CMOS processes, are manufactured at relatively low cost, and are achieve a relatively fast conversion time. In one specific application, such a successive approximation A/D converter is used, for example, as a built-in A/D conversion circuit in a microcontroller (MCU).
When fabricating a successive approximation A/D converter on a CMOS process semiconductor integrated circuit, it is predominantly implemented using a scheme called “charge redistribution” based on a switched-capacitor technique. The reason is that it is relatively easy to achieve a near ideal switch in a CMOS process.
The successive approximation A/D converter performs A/D conversion by sampling an analog voltage, comparing it with the output voltage of an internal DAC (D/A converter: Digital-to-Analog Converter), and conducting a search until finally obtaining a DAC output where the two voltages match most closely. In a basic successive approximation A/D converter, the search is performed using an algorithm (binary search) that iteratively performs the process for obtaining the midpoint of a section known to contain the answer.
In the case of a charge distribution successive approximation A/D converter fabricated without trimming, the resolution that are achieved is generally 12 bits at the most, due to a mismatch of capacitive elements that occurs during the fabrication. It is known that higher resolutions, for example, resolutions of 14 bits and higher, are be achieved by using self-calibration techniques.
First, of successive approximation A/D converters having a single-ended or differential structure, those having higher resolutions are achieved by using, for example, self-calibration techniques.
In a single-ended A/D converter, the offset of the comparator may not be completely removed due to the effects of switch charge injection. Since the offset error caused by the charge injection only seems to shift the conversion characteristic of the A/D converter in one direction, it may not present a problem in some applications.
However, it is difficult to predict how much charge injection occurs and in what situation, and therefore, there has been the problem that the offset error may become one of circuit uncertainties.
This is a problem that affects the A/D conversion process, but in the case of an A/D converter employing a self-calibration technique, the comparator offset gives rise to another problem when measuring capacitive element errors.
More specifically, since the comparator offset that occurs when measuring the errors acts so as to shift the capacitor mismatch by the amount of the offset, it is not possible to measure the errors accurately. As a result, the self-calibration is not done properly, thus causing a problem that limits the accuracy of the A/D converter.
On the other hand, in the case of an A/D converter having a differential structure, compared with the single-ended A/D converter, the advantage is that the influence of the switch charge injection occurring when ending the sampling in the A/D conversion process may be reduced and, hence, the comparator offset may be reduced.
However, no disclosure is made about the circuit structure that may be employed in order to minimize the comparator offset when measuring the capacitor mismatch in the A/D converter having a self-calibration function. In the self-calibration successive approximation A/D converter, the error caused by the comparator offset presents a greater problem when measuring the capacitor mismatch than when performing the A/D conversion.
Here, to implement a charge distribution A/D converter on a semiconductor chip (integrated circuit), not only the MOSFETs implementing the logic gate functions but also the capacitive elements used in the capacitive main DAC and the comparator, for example, may be implemented on the integrated circuit.
For example, to achieve a 14-bit or higher resolution A/D converter, the voltage dependence of the capacitive elements forming the capacitive main DAC may be made small enough to achieve the 14-bit resolution, but this employs the use of, for example, PIP capacitors or MIM capacitors.
However, since PIP or MIM capacitors employ additional fabrication steps, etc. for forming these capacitors, the manufacturing cost increases.
In the comparator also, capacitive elements (coupling capacitors) are used for coupling between differential circuits. Here, it becomes preferable to reduce the parasitic capacitance associated with the coupling capacitors; in particular, the parasitic capacitance of the coupling capacitor provided between the first- and second-stage differential circuits may be made sufficiently small. The reason is that, while it is desired for the comparator to sense very small potential differences at high speed, the parasitic capacitance becomes a primary factor that limits the speed.
More specifically, while it is desired to form the coupling capacitors of the comparator, for example, from MIM capacitors having reduced parasitic capacitance and capable of high-speed operation, this employs additional fabrication steps, etc. and increases the manufacturing cost, as described above.
In the related art, various types of A/D converter have been proposed for implementing the successive approximation A/D converter or the charge redistribution successive approximation A/D converter.    Patent Document 1: Japanese Laid-open Patent Publication No. 2009-232281    Patent Document 2: Japanese Laid-open Patent Publication No. S59-083418    Patent Document 3: Japanese Laid-open Patent Publication No. 2004-032089    Patent Document 4: Japanese Laid-open Patent Publication No. 2007-142863    Patent Document 5: U.S. Pat. No. 4,129,863    Patent Document 6: U.S. Pat. No. 4,200,863    Patent Document 7: U.S. Pat. No. 6,985,101    Patent Document 8: Japanese Laid-open Patent Publication No. H06-085562    Patent Document 9: Japanese Laid-open Patent Publication No. H09-069761    Patent Document 10: Japanese Laid-open Patent Publication No. 2001-144556    Non-Patent Document 1: T. Tsukada, K. Takagi, Y. Kita, M. Nagata, “An automatic error cancellation technique for higher accuracy A/D converters”, Electronics and Communications in Japan, Scripta Publishing Co., vol. 66, no. 11, 1983    Non-Patent Document 2: T. Tsukada, K. Takagi, Y. Kita, M. Nagata, “An automatic error cancellation technique for higher accuracy A/D converters”, IEEE J. Solid-State Circuits, vol. SC-19, no. 2, 1984    Non-Patent Document 3: H. S. Lee, D. A. Hodges, “Self-Calibration technique for A/D converters”, IEEE Transactions on Circuits and Systems, Vol. CAS-30, No. 3, March, 1983    Non-Patent Document 4: H. S. Lee, D. A. Hodges, P. R. Gray, “A Self-Calibrating 15 Bit CMOS A/D Converter”, IEEE Journal of Solid-State Circuits Vol. SC-19, No. 6, December 1984    Non-Patent Document 5: THEODORE L. TEWKSBURY, HAE=SEUNG LEE, GERALD A. MILLER, “The Effects of Oxide Traps on the Large-Signal Transient Response of Analog MOS Circuits”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, April 1989    Non-Patent Document 6: Ka Y. Leung, Kafai Leung, Douglas R. Holberg, “A Dual Low Power ½LSB INL 16b/lMsample/s SAR A/D Converter with on-chip Microcontroller”, Asian Solid-State Circuits Conference, Digest of Technical papers, 2006    Non-Patent Document 7: Jiren Yuan, Christer Svensson, “A 10-bit 5-MS/s Successive Approximation ADC Cell Used in a 70-MS/s ADC Array in 1.2 um CMOS”, IEEE Journal of Solid-State Circuits, Vol. 29, No. 8, August 1994    Non-Patent Document 8: Kouichi Satou, Kazuhiro Tsuji, Masayuki Sahoda, Tetsuya Iida, “A 12b 1 MHz ADC with 1 mW Power Consumption”, Technical Report of IEICE, ICD94-46, pp. 9-16, 1994    Non-Patent Document 9: Kouichi Satou, Kazuhiro Tsuji, Masayuki Sahoda, Hiroshi Otsuka, Kyoko Mori, Tetsuya Iida, “A 12b 1 MHz ADC with 1 mW Power Consumption”, IEEE 1994 Custom Integrated Circuits Conference, 1994